Physical Design Engineer

EXPERIENCE: 3-5 years in ASIC/SoC physical design implementation
ROLES AND RESPONSIBILITIES:
* Execute block-level physical design implementation from netlist to GDS including floorplanning, placement, clock tree synthesis, and routing
* Perform timing closure activities to meet setup and hold requirements across multiple corners and modes
* Collaborate with front-end teams to resolve design issues and ensure smooth design handoff
* Conduct power grid analysis and optimize power distribution networks for IR drop and EM compliance
* Generate and implement ECOs to address timing, power, and physical violations
* Coordinate with physical verification team to ensure DRC/LVS clean signoff
* Create and maintain design documentation, scripts, and methodologies