RTL Engineer

Understanding of IP design, RTL coding, Verilog/SV
Proficient in RTL simulation tools
Knowledge of High-speed interfaces PCIe, Ethernet, DDR AMBA AXI/AHB/APB Protocol
Strong knowledge of IP/SOC design methodologies
Experience with scripting languages including Perl, Python, Unix shells and Makefiles
Excellent communication skills and experience working with global teamsSetup ASIC QA flows for RTL design quality checks.
Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains
Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps.
Clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers.
Checking the flow errors, design errors & violations and reviewing the reports.
Debugging CDC, RDC issues and propose the RTL fixes.